Overview
The 3G Large Depth Vector Signal Generator by EnTegra Ltd, enables
UMTS Engineers to generate 3G baseband signals at 16x chip rate
(61.44MSPS) from IQ samples in files or from EnTegra’s Uplink and
Downlink generators. Since the data is output direct from disk, the
waveform can be as long as the disk system will support, easily in
excess of 3 hour’s of data. Applications include:
- Verification of receiver and transmitter designs against very
large datasets
- Testing Third Party Datasets
- Conformance / Acceptance Testing
PC Based Instrument
The Vector Signal Generator (VSG) is built around a standard
Personal Computer and a bespoke DSP PCI card. The DSP card and
daughter module upsamples and filters the 3.84MSPS IQ pairs using Root
Raised Cosine (RRC) Finite Impulse Response (FIR) filters to
61.44MSPS, which is then output to a pair of 14 bit Digital to
Analogue Converters. The PC runs the MicroSoft Windows 2000 Operating
System and the VSG is driven via a windows application. The Instrument
is available in either a Mini Tower case or 19 inch rack mount 2U
case.
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Uplink & Downlink Generators
The VSG packages the EnTegra 3G technology for Uplink & Downlink
Transmit used within SystemView by Elanix and Microwave Office by
Advanced Waveform Research. The Uplink block performs a complete
standard compliant 3GPP uplink. A Dedicated Traffic Channel (DTCH) and
a Dedicated Control Channel (DCCH) are either generated internally or
read from external files. These two transport channels are then
subject to transport channel coding followed by transport channel
multiplexing and second interleaving. The result is referred to a
Dedicated Physical Data Channel (DPDCH). A Dedicated Physical Control
Channel (DPCCH) is also generated internally. The coded DPDCH and
DPCCH are both channelised and weighted according to the relevant
dialogue parameters. The complex signal is then generated and
scrambled using either long or short codes. The Downlink block
performs a complete standard compliant 3GPP downlink. The following
channels are generated, P-SCH, S-SCH, P-CPICH and S-CPICH, PICH,
P-CCPCH and S-CCPCH. The Dedicated Phyiscal Channel (DPCH) is also
generated with full control over the transport channel coding.
Analogue or Digital Outputs
The output which is at 61.44MSPS can be from 14 bit Digital to
Analogue converters or 12 bit digital LVDS via a front panel
connector. The analogue IQ output is a peak of -3dBm into 50 ohms.
DC Offset Control
The digital samples each have DC offset correction applied which is
set under user control.
Frequency Shifted Outputs
The IQ output may be shifted in frequency by ±20MHz using a
numerically controlled oscillator, with a resolution of 0.02Hz.
10MHz Reference
The VSG can be clocked using either it’s own temperature controlled
10MHz reference or an external 10MHz reference clock. |
