TMS320C6701 (C6701) DSP
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Boards Using the TMS320C6701

TMS320C6701 DSP Description

The TMS320C67Ô..DSPs are the floating-point DSP family in the TMS320C6000E DSP platform. The TMS320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

 

PARAMETER NAME TMS320C6701-160
Cycle Time (ns) 6
Data/Program Memory (bits) 512K/512K
DMA 4
External Memory Interface (1) 32-bit
Host Port / Exp. Bus / PCI HPI 16-bit
McBSP 2
Timers (2) 32-bit
Core Supply (Volts) 1.9
IO Supply (Volts) 3.3
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • 150-, 167-MHz Clock Rate
    • 900-MFLOPS, 1 GFLOPS
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
    • Six ALUs (32-/40-Bit)
    • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • 1M-Bit On-Chip SRAM
  • 32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
  • Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With anAuxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • 352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
    • TMS320C6201 Fixed-Point DSP Pin-Compatible

VelociTI is a trademark of Texas Instruments

VelociTI and TMS320C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C67x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.