Atropos. Precision Timing for Sample clock generation and Triggering

20 Years Experience

Atropos sample clock timing generator for clock generation
http://www.innovative-dsp.com/

Precision Timing for Sample Rate Generation and Triggering Controls with high precision reference

FAQ
Made in USA, sold and supported in UK.
  • Sample clock generation and distribution
  • Four single-ended clock outputs
  • External clock/reference input
  • Low noise: 91 fs RMS jitter -162.5 dBc/Hz noise floor (fc=245.76 MHz)
  • Programmable 70.06 to 3080 MHz range
  • On-board 10 MHz, 250 ppb oscillator or
  • External frequency reference
  • Four programmable trigger outputs
  • Supports J16 triggers and local bus
  • External trigger input
  • XMC Module (75×150 mm)
  • PCI Express (VITA 42.3)

Atropos is an XMC I/O module with precision, low-noise sample clock generation and distribution for data acquisition and communications timing applications. The module has four output clocks and four output triggers as well as a clock/reference input and a trigger input. The Atropos can also act as a system timing card in multi-board XMC, FMC or PCIe -based systems, providing the reference clock, sample clocks and triggering.

In the sample clock generation mode, the Atropos can generate clocks from 70.06 to 3080 MHz *. All clock outputs may be referenced to an on-card 280 ppb temperature-compensated oscillator, or an external clock input.

The PLL circuit is fully programmable, providing extremely low noise clocks with 91 fs RMS jitter, -162.5 dBc/Hz noise floor (fc=245.76 MHz). The output clocks are phase aligned to within 100 ps. Each output clock is a 1 to 32 subdivision of the external clock or second- stage PLL, which may programmatically operate in either the 2370- 2630 or 2920-3080 MHz* range.

* Please check with us which frequency(s) you need to run the clock at because there are gaps in the frequency range.

Windows and Linux applications are provided that are used to configure and control all Atropos features.

Software tools for host development include C++ libraries and drivers for Windows and Linux.

  • PLL = LMK04828
  • Sample clock generation for high speed data acquisition applications
  • Sample clock generation for multi-channel systems
  • Synchronization for distributed systems
  • GPS-coordinated systems
  • Timing Generation (Analog cover and heatsink removed.)

Application Notes