V616 Digital Transceiver: Four Independent 16 bit DDC channels and two independent 16 bit DUC channels, based on X6-1000M

20 Years Experience

ePC-Duo embedded pc with dual XMC sites, 10G ethernet, SATA etc

Ready programmed Digital Transceiver Instrument based on X6-1000M.

Made in USA, sold and supported in UK.
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  • Intel i7 Quad Core, 16 GB RAM, 240 GB SSD, dual 10 GbE, Win 7 Pro 64-bit
  • Two, independent XMC module sites
  • Sustained logging rate up-to 2,000 MByte/s

Per-Module Features

  • Two 12-bit, 1000 MHz ADCs; analog bandwidth: 1000 MHz (AC Coupled)
  • Two 16-bit, 1000 MHz DACs; analog bandwidth: 1000 MHz (AC Coupled)
  • Xilinx Virtex-6 SX475T-2 FPGA
  • Embedded power meter
  • PCI Express Gen 2 (3,600 MByte/s)

Digital Down-Converter (DDC)

  • Four independent 16-bit DDC channels
  • Programmable tuner: 1 – 1000 MHz; resolution 0.2328 Hz
  • Programmable bandwidth: 10 KHz – 100 MHz
  • DDC outputs SNR >64dB; SFDR >80dB
  • Spectrum inversion for ADC under-sampling
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger

Digital Up-Converter (DUC)

  • Two independent 16-bit DUC channels
  • Programmable tuner: 1 – 1000 MHz; resolution 0.2328 Hz
  • Programmable bandwidth: 10 KHz – 100 MHz
  • Spectrum inversion

Spectrum Analyzer

  • Single wide-band/narrow-band 32K points FFT
  • Eight Windowing available
  • Programmable FFT update rate
  • Programmable maximum hold mode
  • Threshold limited spectrum monitoring up-to 512 bins

The V616 digital transceiver supports one or two plug-in modules, each featuring four independent channels of DDC, two DUC, and one spectrum analyzer embedded in the Xilinx Virtex-6 FPGA. It allows users to monitor the wide-band or narrow band spectrum and record the data directly from the ADCs or down-convert the channels modulated on the IF band. The embedded PC can do contiguous recording at 2,000 MByte until running out of disk space. The transmitter can play the recorded baseband waveform of different bandwidth, up-convert and modulate it on the IF band on the DACs.

Each DDC/DUC has its own programmable tuner, programmable low-pass filtering, gain control, and decimation/interpolation setting, supporting independent channel bandwidths up-to 100 MHz. The DDC data is packetized in VITA-49 format with the accurate timestamps, synchronous to the external PPS signal. The DDC channel can be enabled and disabled on the fly to save the storage and bandwidth to the host computer. The embedded power meter monitors the power (dBFS) of the ADC inputs, allowing users to perform possibly analog gain control in the external front-end device, not included in the system.

The spectrum analyzer, including windowing, calculates the wide- band spectrum of the ADC data or the narrow-band spectrum of the DDC output data at the programmable update rate. The maximum hold helps to retain the information in the spectrum and the programmable threshold monitoring spectrum detects the spectral activities up-to 512 bins.

A development kit is available for the custom design. Users can insert custom-made cores to create even more advanced applications.

  • Analogue to Digital Converter(s) = TI ADS5400
  • FPGA = Xilinx Virtex6 XC6VSX475T
  • Digital to Analogue = TI DAC5682Z
  • Digital Receiver/Recorder
  • Spectrum Analysis
  • Surveillance
  • Software Defined Radio
  • Arbitrary waveform generator/player