FMC-SDF Data Acquisition board with four AD7763 625kSPS ADCs and two LTC2758 476kSPS DACs on FMC

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FMC-SDF Data Acquisition board with four AD7763 625kSPS ADCs and two LTC2758 476kSPS DACs on FMC
http://www.innovative-dsp.com/

FMC HPC Module with 4x 625 kSPS 24-bit Adc’s and 2x 2.1us settling time 18-bit DAC’s with PLL and Timing Controls

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Made in USA, sold and supported in UK.
FMC Carriers
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  • Four A/D Input Channels
    • ± 5V Input Range
    • 625 kSPS, 24-bit A/D
    • Differential
  • Two D/A Output Channels
    • 2.1µs Settling Time, 18-bit D/A
    • ± 5V Output Range
  • Tachometer Input
    • Schmitt-Triggered for glitch tolerance
    • Can be configured to operate differentially
  • Sample clocks and timing and controls
    • 10 MHz, ±250 ppb stability on-board reference.
    • Programmable PLL
    • Programmable Clock Frequency as low as 3.05 kHz
    • Integrated with FMC triggers
  • FMC module, VITA 57.1
    • High Pin Count no SERDES required
    • Compatible with 2.5V VADJ
    • Power monitor and controls
  • 15 W typical
  • Conduction Cooling per VITA 20 subset
  • Environmental ratings for -40 to 85C
  • 9g RMS sine, 0.1g2/Hz random vibration

The FMC-SDF module features four simultaneously sampling ADCs and DACs with an FPGA computing core. High resolution sigma-delta ADCs and high resolution DACs support high dynamic range applications such as audio, ATE, and seismic data acquisition.

Clock and trigger controls include support for consistent servo loop timing, counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source.

The FMC-SDF power consumption is 15 W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation are available from -40 to +85C operation and 0.1 g2/Hz vibration. Conformal coating is also available.

Support logic in VHDL is provided for integration with FPGA carrier cards. Specific support for Innovative carrier cards includes integration with Framework Logic tools that support VHDL and Matlab developers. The Matlab BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator for the FMC integrated with the FPGA carrier card.

Software tools for Innovative carrier cards include host development C++ libraries and drivers for Windows and Linux, 32/64-bit including RTOS variants. Application examples demonstrating the module features are provided.

*Sampling rates in an application depend on carrier and system design.

  • Analogue to Digital Converter(s) = Analog Devices AD7763
  • FPGA = None, on host board
  • Digital to Analogue = Linear Technology LTC2758

The FMC modules come with logic to use them on the Innovative FMC hosts (ePC-K7, mini-K7, Cardsharp, COPious-PCIe, COPious-PXIe & others). The logic includes a sample streaming interface to the system processor. Please see the data flow diagram for the generic model.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

The FMC host memory is usually 256MB or more. If the host can not consume the data as fast as the Adc(s) produces it, the memory fills with samples. This defines the longest continuous capture length possible.

The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.

  • Seismic Data Acquisition
  • Audio and Acoustic Testing
  • ATE
  • Other High SNR Data Acquisition