Embedded PC for Instrumentation and Control with a Kintex7 FPGA Core and Configurable FMC Host IO
- Embedded PC
- Runs Windows or Linux
- (i7 CPU 4 cores, 2.2GHz, 8-16GB) or (Atom CPU 1 or 2 cores 1.6GHz 2GB)
- USB, GbE, SATA, IEEE1588
- Touchscreen LCD and displayport support
- Removable SDHC boot drive
- Small and low power
- 200 x 160 x 30mm
- <30W (Atom), <70W (i7), not inc FMC.
- Conduction or air cooled version
- FMC I/O Sites
- Dual VITA 57 Module sites
- Site 0 is a HPC site
- Site 1 is a LPC site
- 8 lanes, 6.5Gbps (x4 with shared Ethernet)
- FPGA Computing Core
- Xilinx Kintex7 K160T, K325T, or K410T
- 2 memory banks: up to 1GB LPDDR2 DRAM or 8MB QDRII SRAM each
- Communication Ports
- 10Gb Ethernet with SFP+ fiber optic port
- “Wire Speed” rates support 1GB/s streaming
- Timing Features
- IEEE 1588 and IRIG timing synchronization
- Optional GPS integration
- Clock and trigger I/O for system timing
- Environmental ratings for -40 to 85C and 5g vibe
The SBC-K7 FMC Host is an ideal platform for embedded instrumentation that combines an Atom/i7 PC running Windows or Linux with a Xilinx Kintex7 FPGA and an industry-compliant FMC IO site (HPC) plus a second FMC-compatible (LPC) site.
The CPU is a COM Express module featuring an Intel i7 processor that is a fully compatible PC. The COM Express is optimized for processing power and has Ethernet, USB, SATA, DisplayPort, touchscreen LCD and PCI Express connectivity. The COM Express module is industry-standard, multi-sourced with a range of performance/power choices.
The FPGA computing core features the Xilinx Kintex 7 FPGA family, from K160T to K410T. The K410T provides 1540 DSP MAC elements operating at up to 500 MHz and 400K logic cells. The FPGA core has two memory banks, each of which is either up to 1GB LPDDR2 DRAM or 8MB QDRII SRAM.
FMC Host I/O site0 has 80 LVDS pairs connected to the FPGA, plus clocks, controls, and up to x8 6.5 Gbps lanes. The HPC FMC site can host the FMC-250, FMC-310, FMC-500, FMC-1000 or the FMC-SFP+. The LPC FMC site can host the FMC-10GE. Timing features include clock and trigger I/O for multi-card synchronization. GPS, IEEE 1588 PTP and IRIG-B timing references are integrated with on-card timing features for system-level timing coordination. Innovative offers a full line of FMC analog and digital IO modules or can be readily adapted to custom modules.
For system communications the SBC-K7 includes two, 1Gb Ethernet and 4x USB ports. The 1G Ethernet and USB ports provide instant connectivity to host PCs and networks. A USB client port also allows operation as a USB device. 10 Gb communications can be implemented via an available FMC-SPF+. The 10Gb Ethernet port connects directly to the FPGA, providing sustained “wire speed” rates of ~1GB/s over a fiber optic connection.
The SBC-K7 is rugged and low power. Power consumption is ~20W (K160T FPGA) excluding FMC and operates from a 9-32V input . Air and conduction cooled versions are available rated for -40 to +85C, with up to 5 g vibration.
The FPGA logic can be fully customized using VHDL/Verilog or Matlab using the the Frame Work Logic toolset. Real-time hardware-in-the-loop development using the graphical Simulink block diagrams is supported. IP cores for signal processing applications such down-conversion, demodulation and FFT are also available.
Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrate card use and features.
- Analogue to Digital Converter(s) = N/A
- FPGA = Xilinx Kintex7 K160T, K325T, or K410T
- Digital to Analogue = N/A
The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.
The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.
On Sbc-K7 the Adc memory is 512MB.
The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.
On Sbc-K7 the Dac memory is 512MB.
- Waveform Generation
- Embedded Control
- Remote Data Acquisition
- Industrial Test & Measurement
- OEM Instrumentation