K701: 8 Independent Wideband Digital Receiver Channels with FFT, based on FMC-250 & ePC-K7

20 Years Experience

K701 Digital Receiver with Kintex-7, 250MSPS 16 bit Adcs, host Intel i7 CPU
http://www.innovative-dsp.com/

Ready programmed Wideband Digital Receiver Instrument based on FMC-250.

FAQ
Made in USA, sold and supported in UK.
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  • Two 16-bit, 250 MHz ADCs
  • Analog bandwidth: 5 – 300 MHz (AC Coupled)
  • Xilinx Kintex-7 K410T2 FPGA
  • Intel i7 Quad Core, 16 GB RAM, 256 GB SSD, Win 7 Pro 64-bit
  • Sustained logging rate up-to 1600 MByte/s
  • Embedded power meter

Digital Down-Converter (DDC)

  • Eight independent 16-bit DDC channels
  • Programmable tuner: DC – 125 MHz; resolution 0.0582 Hz
  • Programmable bandwidth: 2 KHz – 50 MHz
  • DDC outputs SNR > 55 dB; SFDR > 75 dB
  • Spectrum inversion for ADC under-sampling
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger
  • Synchronous VITA 49 timestamp

Spectrum Analyzer

  • Single wide-band/narrow-band 32K points FFT
  • Eight Windowing available
  • Programmable FFT update rate
  • Programmable maximum hold mode
  • Threshold limited spectrum monitoring up-to 512 bin

The K701 Wideband Digital Receiver supports one or two plug-in FMC modules each providing up to eight independent channels of DDC and one spectrum analyzer embedded in a Xilinx Kintex-7 FPGA. It allows users to monitor the wide-band or narrow band spectrum and record the data directly from the ADCs or down-convert the channels modulated on the IF band. The receiver can do contiguous recording at 1600 MByte until running out of disk space.

Each wideband digital receiver DDC has its own programmable tuner, programmable low- pass filtering, gain control, and decimation setting, supporting output bandwidth up-to 50 MHz. The data is packetized in VITA 49 format with the accurate timestamps, synchronous to the external PPS signal. The DDC channel can be enabled and disabled on the fly to save the storage and bandwidth to the host computer. The embedded power meter monitors the power (dBFS) of the ADC inputs, allowing users to perform possibly analog gain control in the external front-end device, not included in the system.

The spectrum analyzer, including windowing, calculates the wide- band spectrum of the ADC data or the narrow-band spectrum of the DDC output data at the programmable update rate. The maximum hold helps to retain the information in the spectrum and the programmable threshold monitoring spectrum detects the spectral activities up-to 512 bins.

A development kit is available for custom designs. Users can insert custom-made cores to create more advanced applications.

  • Analogue to Digital Converter(s) = Intersil ISL216P25
  • FPGA = Xilinx Kintex7
  • Digital to Analogue = N/A
  • Digital Receiver/Recorder
  • Spectrum Analysis
  • Surveillance
  • Software Defined Radio