V613: 8 or 16 Independent Wideband Digital Receiver Channels with FFT, based on one or two X6-GSPS & ePC-Duo

20 Years Experience

ePC-Duo embedded pc with dual XMC sites, 10G ethernet, SATA etc
http://www.innovative-dsp.com/

Ready programmed Wideband Digital Receiver Instrument based on X6-GSPS.

FAQ
Made in USA, sold and supported in UK.
Components
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  • Intel i7 Quad Core, 16 GB RAM, 240 GB SSD, dual 10 GbE, Win 7 Pro 64-bit
  • Two, independent XMC module sites
  • Sustained logging rate up-to 2,000 MByte/s

Per-Module Features

  • Two 12-bit, 1800 MHz ADCs
  • Analog bandwidth: 1 – 2500 MHz (AC Coupled)
  • Xilinx Virtex-6 SX475T-2 FPGA
  • Embedded power meter
  • PCI Express Gen 1 (1,300 MByte/s)

Digital Down-Converter (DDC)

  • Eight independent 16-bit DDC channels
  • Programmable tuner: 1 – 1800 MHz; resolution
    0.4191 Hz
  • Programmable bandwidth: 10 KHz – 90 MHz
  • DDC outputs SNR > 55 dB; SFDR > 65 dB
  • Spectrum inversion for ADC under-sampling
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger
  • Synchronous VITA-49 timestamp

Spectrum Analyzer

  • Single wide-band/narrow-band 32K points FFT
  • Eight Windowing available
  • Programmable FFT update rate
  • Programmable maximum hold mode
  • Threshold limited spectrum monitoring up-to 512 bins

The V613 Digital Receiver supports one or two plug-in X6-GSPS modules, each providing up to eight independent channels of DDC and one spectrum analyzer embedded in a Xilinx Virtex 6 FPGA. It supports monitoring and/or recording of wide- or narrow-band spectra or channelized IF band data. The receiver supports contiguous recording at 2,000 MByte/s until running out of disk space.

Each DDC has its own programmable tuner, programmable low- pass filtering, gain control, and decimation setting, supporting independent output bandwidth up-to 90 MHz. Data is packetized in VITA-49 format with accurate timestamps, synchronous to an external PPS signal. Each DDC channel can be enabled or disabled on the fly to save host storage and bandwidth. The embedded power meter monitors the power (dBFS) of the ADC inputs, supporting analog gain control of optional, user-supplied external front-end devices.

The spectrum analyzer, which supports windowing, calculates the wide-band spectrum of raw ADC data or the narrow-band spectrum of the cooked DDC output data at a programmable update rate. A programmable peak hold feature may be enabled to latch transient activity in the spectrum and the programmable threshold monitoring spectrum feature tracks spectral activities of up-to 512 bins.

A development kit is available to facilitate custom designs. Users can insert custom-made cores within the provided Framework to create more advanced applications, including features such as demodulation, decoding and error correction.

  • Analogue to Digital Converter(s) = National ADC12D1800
  • FPGA = Xilinx Virtex6
  • Digital to Analogue = N/A
  • Digital Receiver/Recorder
  • Spectrum Analysis
  • Surveillance
  • Software Defined Radio