X3-25M Data Acquisition Board with 105MSPS LTC2207 Adcs, 50MSPS Dacs and Spartan 3A DSP FPGA

20 Years Experience

X3-25M 2 channels of 105MSPS 16 bit ADC, 2 channels of 50MSPS 16 bit DAC, Spartan3A DSP FPGA and x4 lanes to host.

This product has been superseded by the new XA series, please review that for new projects. 

PCI Express XMC Module, with 2 simultaneous LTC2207 channels of 105 MSPS 16-bit A/D, 2 x 50MSPS 16 bit DAC and 1.8M FPGA with DSP

Made in USA, sold and supported in UK.
  • Two 105 MSPS, 16-bit A/D channels LTC2207
  • Two 50 MSPS, 16-bit DAC channels LTC1668
  • +/-2V, +/-1V, +/-0.2V input ranges
  • +/-2V output range
  • 16-bits front panel DIO (8 differential pairs)
  • Xilinx Spartan 3A,DSP 1.8M gate FPGA
  • 4MB SRAM
  • Programmable PLL timebase
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 44 bits digital IO on J16
  • Power Management features
  • XMC Module (75×150 mm)
  • PCI Express (VITA 42.3)

The X3-25M is an XMC IO module that can be fitted in a PC using a XMC to PCIe adapter or XMC to PCI adapter or a CompactPCI chassis using a XMC to CompactPCI adapter or a Standalone PC. Other hosting options include a standalone eInstrument and connection to a variety of PC hosts.

The data acquisition board has 2 channels of simultaneous 16 bit analogue to digital converters, LTC2207. The maximum sample rate that can be streamed to the host is 90MSPS on a single channel or 45MSPS 2 channels. The analogue inputs have a lowpass filter with cutoff at 75MHz, and a programmable gain amplifier which gives input ranges of +/-2V, +/-1V and +/-0.2V. The converter (LTC2207) is a pipelined successive approximation device.

The converters have a maximum conversion rate of 105MSPS but the interface to the onboard memory can only sustain ~180MB/s in and out functioning as a FIFO to the host. Therefore the converters can only be run above 90MSPS if a) only 1 channel is used, or b) if user logic is inserted to the data flow before the memory interface which decimates the data. For example a digital downconverter.

The board also has 2 channels of simultaneous 16 bit digital to analogue converters. These can be clocked at upto 50MSPS and have filters which give a 12.5MHz bandwidth and voltage range +/-2V. If streaming from the host via the memory direct to the DACs be aware that few hosts are able to sustain 180MB/s to XMC boards. The board can also be used to preload waveforms in the memory and play at full rate for a burst.

The X3-25M has an onboard PLL which can be driven by an onboard reference oscillator or by an offboard reference clock. Alternately the user can supply an external clock. Triggering of the start of samples can be done by software or an external active high LVTTL signal.

The X3-25M also has 44 bits of user digital IO. This can be read or written to as a 32 bit register from the host, or if the user modifies the logic, can be used to interface to a variety of digital devices such as serial, parallel ports, I2C devices etc. The Spartan3 device supports LVTTL.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA, 1.8M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory. The data acquisition board has a single lane PCI Express interface to the host which can sustain 160MB/s to the host.

The X3-25M is supported by Malibu, a set of C++ libraries to use the board under Windows and Linux. This includes example programs to use the board to setup the logic, acquire samples and stream them to disk, and a Wave program to stream samples from host to Dacs.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

  • Analogue to Digital Converter(s) = LTC2207
  • FPGA = Xilinx Spartan3A DSP – XC3SD1800A
  • Digital to Analogue = LTC1668

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X3-25M the Adc memory is 2MB.

The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.

On X3-25M the Dac memory is 2MB.

  • Wireless Receiver and Transmitter
  • Stimulus-response measurements
  • Electronic Counter Measures (ECM)
  • High speed servo controls
  • Arbitrary Waveform Generation
  • Spectral Analysis

These videos may be helpful in learning about using the FPGA on this board.