X3-2M Data Acquisition Board with 12 simultaneous channels of 10 MSPS 16-bit A/D, and 1.8M FPGA with DSP

20 Years Experience

X3-2M Data Acquisition board with 12 channels of 10MSPS 16 bit Adcs, Xilinx Spartan3A DSP FPGA, x4 lane PCIe to host.
http://www.innovative-dsp.com/

This product has been superseded by the new XA series, please review that for new projects. 

PCI Express XMC Module, with 12 simultaneous channels of 10 MSPS 16-bit A/D, and 1.8M FPGA with DSP

FAQ
Made in USA, sold and supported in UK.
  • 12 channels of 10 MSPS, 16-bit simultaneously sampling A/D
  • -110 dB noise floor, 91 dB SFDR
  • Low latency SAR converters
  • 50 ohm, differential inputs
  • Continuously acquire 12 simultaneous
  • channels at 10 MSPS to system memory
  • Stream to system memory at up to 220MB/s
  • Xilinx Spartan3A DSP, 1.8M gate FPGA
  • 4MB SRAM
  • Sample clock is external or programmable, low jitter PLL
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 6 LVDS digital IO pairs on Front Panel
  • 44 bits digital IO on P16
  • Power Management features
  • PCI Express XMC Module (75×150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, or cabled PCI Express application

The X3-2M module is easily adapted for use in virtually any type of system. Our XMC carrier adapters offer conduction and convection cooling and are available for a range of interfaces including Desktop PCI, Desktop PCI Express, Cabled PCI Express, CompactPCI, and PXI/PXI Express. This module is also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.

The data acquisition board has 12 channels of simultaneous 16 bit analogue to digital converters. The maximum sample rate that can be streamed to the host is 9MSPS all 12 channels. The analogue inputs have a lowpass filter with cutoff at 25MHz, and an input range of +/-2V. The converter (AD7626) is a pipelined successive approximation device.

The converters have a maximum conversion rate of 10MSPS but the interface to the onboard memory can only sustain ~220MB/s in and out functioning as a FIFO to the host. Therefore the converters can only be run above 9MSPS if a) only 10 channels or less are used, or b) if user logic is inserted to the data flow before the memory interface which decimates the data. For example a digital downconverter.

The X3-2M has an onboard PLL which can be driven by an onboard reference oscillator or by an offboard reference clock. Alternately the user can supply an external clock. Triggering of the start of samples can be done by software or an external active high LVTTL signal.

The X3-2M also has 44 bits of user digital IO. This can be read or written to as a 32 bit register from the host, or if the user modifies the logic, can be used to interface to a variety of digital devices such as serial, parallel ports, I2C devices etc. The Spartan3 device supports LVTTL.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA, 1.8M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory. The data acquisition board has a four lane PCI Express interface to the host which can sustain 220MB/s to the host.

The X3-2M is supported by Malibu, a set of C++ libraries to use the board under Windows and Linux. This includes example programs to use the board to setup the logic, acquire samples and stream them to disk.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

  • Analogue to Digital Converter(s) = AD7626
  • FPGA = Xilinx Spartan3A DSP – XC3SD1800A
  • Digital to Analogue = N/A

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X3-2M the Adc memory is 4MB.

  • Electronic Counter Measures (ECM)
  • Neuro-physical instrumentation
  • High speed motion recording
  • Spectral Analysis
  • RADAR

These videos may be helpful in learning about using the FPGA on this board.