PCI Express XMC Module, 4 Channel, 4 MSPS successive approximation A/Ds, 4 channel 50 MSPS DACs and 1.8M Spartan3A DSP FPGA
- Servo Loop Controller
- Four 4 MSPS, 16-bit A/D channels
- Four 50 MSPS, 16-bit DAC channels
- +/-10V, +/-5V, +/-2.5V, +/-1.25V input ranges
- +/-10V output range
- Low Latency I/O
- Xilinx Spartan3A DSP, 1.8M gate FPGA
- 4MB SRAM
- Programmable PLL timebase
- Framed, software or external triggering
- Log acquisition timing and events
- 48 bits digital IO on J16
- Power Management features
- XMC Module (75×150 mm)
- PCI Express (VITA 42.3)
The X3-A4D4 servo loop module is easily adapted for use in virtually any type of system. Our XMC carrier adapters offer conduction and convection cooling and are available for a range of interfaces including Desktop PCI, Desktop PCI Express, Cabled PCI Express, CompactPCI, and PXI/PXI Express. This module is also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.
The data acquisition board aimed at Servo Loop Control applications has 4 channels of simultaneous 16 bit analogue to digital converters at 4MSPS. The analogue inputs have a lowpass filter with cutoff at 600kHz, and a programmable gain amplifier which gives input ranges of +/-10V, +/-5V, +/-2.5V and +/-1.25V. The converter (ADS8442) is a successive approximation device.
The board also has 4 channels of simultaneous 16 bit digital to analogue converters. These can be clocked at upto 50MSPS and have filters which give a 2.5MHz bandwidth and voltage range +/-10V.
The X3-A4D4 servo loop controller has an onboard PLL which can be driven by an onboard reference oscillator or by an offboard reference clock. Alternately the user can supply an external clock. Triggering of the start of samples can be done by software or an external active high LVTTL signal.
The X3-A4D4 also has 44 bits of user digital IO. This can be read or written to as a 32 bit register from the host, or if the user modifies the logic, can be used to interface to a variety of digital devices such as serial, parallel ports, I2C devices etc. The Spartan3 device supports LVTTL.
Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA, 1.8M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory. The data acquisition board has a single lane PCI Express interface to the host which can sustain 160MB/s to the host.
The X3-A4D4 is supported by Malibu, a set of C++ libraries to use the board under Windows and Linux. This includes example programs to use the board to setup the logic, acquire samples and stream them to disk, and a Wave program to stream samples from host to Dacs.
The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.
- Analogue to Digital Converter(s) = TI ADS8442
- FPGA = Xilinx Spartan3A DSP – XC3SD1800A
- Digital to Analogue = LTC1668
The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.
The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.
On X3-A4D4 the Adc memory is 2MB.
The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.
On X3-A4D4 the Dac memory is 2MB.
- Servo Loop Controller
- Servo Controls
- Stimulus-response measurements
- Arbitrary Waveform Generation