X3-DIO Data Acquisition Board with 64/32 bit LVTTL/LVDS and FPGA

20 Years Experience

X3-DIO for digital interface applications with a Spartan 3A FPGA, virtual FIFO using SRAM to and from host via x1 PCIe.

PCI Express XMC Module, with 64/32 bit LVTTL/LVDS and Spartan3A DSP 1800k FPGA

Made in USA, sold and supported in UK.
  • DIO Data Acquisition
  • 64 single-end/32 differential digital IO
  • 100 MHz signal rates to FPGA using LVDS
  • 50 MHz LVCMOS signal rates
  • 400 MB/s LVDS capture/playback to SRAM
  • Optional on-card termination
  • Xilinx Spartan3A DSP, 1.8M gate FPGA
  • 4MB SRAM
  • External clocking and triggering
  • Programmable timebase
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 48 bits digital IO on J16
  • Power Management features
  • XMC Module (75×150 mm)
  • PCI Express (VITA 42.3)

The X3-DIO data acquisition module is easily adapted for use in virtually any type of system. Our XMC carrier adapters offer conduction and convection cooling and are available for a range of interfaces including Desktop PCI, Desktop PCI Express, Cabled PCI Express, CompactPCI, and PXI/PXI Express. This module is also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.

The X3-DIO is for high speed digital IO data interfaces featuring 64bits of front-panel digital IO. The DIO is either single-ended LVCMOS or LVDS differential pairs. The DIO is directly connected to the FPGA, supporting high speed pattern generation, digital recording, custom IO interfaces and control applications.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP, 1.8M gate device. Two 512kx32 memories are used for data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express 4 lane interface supports continuous data rates up to 220 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.

  • Analogue to Digital Converter(s) = N/A
  • FPGA = Xilinx Spartan3A DSP – XC3SD1800A
  • Digital to Analogue = N/A

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X3-DIO the input memory is 4MB and is shared with the output memory.

The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.

  • Pattern Generation
  • Custom Digital Interfaces for Remote IO
  • Digital Controls

These videos may be helpful in learning about using the FPGA on this board.