PCIe XMC Module – Two 1 GSPS Adcs, 12-bit TI ADS5400’s and Two 1 GSPS, 16-bit DACs, Virtex6 FPGA and 4 GB Memory
- Two 1 GSPS Adc’s (1000 MSPS), 12-bit ADC channels
- Two 1 GSPS Dac’s (1000 MSPS), 16-bit DAC channels/ Four 500 MSPS, 16-bit DAC channels
- Xilinx Virtex6 SX315T/SX475T or LX240T
- 4 Banks of 1GB DRAM (4 GB total)
- ADS5400 ADC’s
- DAC5682Z DAC’s
- Ultra-low jitter programmable clock
- Gen2 x8 PCI Express providing 2 GB/s sustained transfer rates
- PCI 32-bit, 66 MHz with P4 to Host card
- PMC/XMC Module (75×150 mm)
- 18-25W typical
- Conduction Cooling per VITA 20
- Environmental Levels for -40 to 85C operation, 9g RMS sine, 0.1g2/Hz random vibration
- Adapters for VPX, Compact PCI, desktop PCI and cabled PCI Express systems
The X6-1000M Data Acquisition Board integrates high-speed digitizing and signal generation with signal processing on a PMC/XMC IO board module for demanding DSP applications. The tight coupling of the digitizing to the Virtex6 FPGA core realizes architectures for SDR, RADAR, and LIDAR front end sensor digitizing and processing. The PCI Express system interface sustains transfer rates over 2 GB/s for data recording and integration as part of a high performance realtime system.
The X6-1000M features two 12-bit 1000MSPS ADCs, either AC or DC-coupled (specify at time of order). The input voltage range is +/-1V and 50 ohms impedance. The AC coupled variant has an input bandwidth of 5MHz to 750MHz. The DC coupled variant has an input bandwidth of DC to 1000MHz.
The Digital to Analogue output channels are implemented using a pair of TI DAC5682Z which is a dual 500MSPS or single 1GSPS 16 bit device. Therefore the X6-1000M can be used as 4 outputs upto 500MSPS or 2 outputs upto 1GSPS. The DAC includes interpolation modes. The outputs are either AC or DC coupled (specify at time of order). The AC coupled variant bandwidth is 5MHz to 1000MHz. The DC coupled variant bandwidth is DC to 1000MHz.
A Xilinx Virtex6 SX315T (LX240T and SX475T options) with 4 banks of 1GB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates. The X6-1000M power consumption is 20W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation from -40 to +85C operation and 0.1 g2/Hz vibration. Conformal coating is available.
The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic tool set. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless, DSP and RADAR functions such as large-scale preintegrator, DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available. Software tools for host development include C++ libraries and drivers for Windows, Linux and VxWorks. Application examples demonstrating the module features are provided.
The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.
The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.
On X6-1000M the Adc memory is 2GB.
The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.
On X6-1000M the Dac memory is 2GB.
- Wireless Receiver and Transmitter
- Quantum Computing
- LTE, WiMAX Physical Layer
- Medical Imaging
- High Speed Data Recording and Playback
- IP development
The product comes with the following support items to help you with your project:
- Malibu Software, including
- Arb, Snap, Wave & Stream – example applications as sourcecode to setup the board for acquisition and waveform generation. Shows designer how to stream Adc samples to host file and stream from host to Dacs, written in C++.
- Drivers for Windows/Linux, 32 and 64 bit.
- Framework logic (source is extra cost)
- Makes the X6 board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
- Knowledgebase of previous users of the X6 board.
- Access to the X6 engineers.
- Full hardware, software and firmware manuals as PDF.
- Telephone/email technical support from EnTegra DSP and Innovative Integration.