X6-250M Data Acquisition Board with LTC2157-14 ADCs and Virtex6 FPGA all on XMC

20 Years Experience

X6-250M - Eight 250MSPS 14-bit Adcs with Virtex6 240/315/475 FPGA, 4GB DRAM and PCIe x8 lanes Gen2
http://www.innovative-dsp.com/

PCIe XMC Module – Eight 250 MSPS, 14-bit LTC2157-14 ADCs, Virtex6 FPGA and 4 GB Memory. 310MSPS, 14 bit version available.

FAQ
Made in USA, sold and supported in UK.
  • Eight 250 MSPS, 14-bit ADC channels (optional 310 MSPS 14 bit)
  • Xilinx Virtex6 SX315T/SX475T or LX240T
  • 4 Banks of 1GB DRAM (4 GB total)
  • LTC2157-14 or LTC2158-14 ADC’s
  • Ultra-low jitter programmable clock
  • Gen2 x8 PCI Express providing 2 GB/s sustained transfer rates
  • PCI 32-bit, 66 MHz with P4 to Host card
  • PMC/XMC Module (75×150 mm)
  • 18-25W typical
  • Conduction Cooling per VITA 20
  • Environmental Levels for -40 to 85C operation, 9g RMS sine, 0.1g2/Hz random vibration
  • Adapters for VPX, Compact PCI, desktop PCI and cabled PCI Express systems

The X6-250M Data Acquisition Board integrates digitizing with signal processing on a PMC/XMC IO module. The module has a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. Applications include software-defined radio, RADAR receivers, and multi-channel data recorders.

The X6-250M has eight simultaneously sampling A/D (LTC 2157-14) channels that sample at rates up to 250 MSPS (14-bit). The A/D have matched input delays and response. The board is available as either AC or DC coupled inputs. The AC variant has an input bandwidth of upto 400MHz, the DC variant has an input bandwidth of up to 550MHz. The A/D are supported by a programmable sample clock PLL and triggering that support multi-card synchronization for large scale systems.

A Xilinx Virtex6 SX315T (LX240T and SX475T options) with 4 banks of 1GB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates.

The X6-250M has both XMC and PCI interfaces, supporting PCI Express or older PCI systems. The PCI Express interface provides up to 2 GB/s sustained transfers rates through a x8 PCIe Gen2 interface.

System expansion is supported using secondary PCI Express or Aurora port used as a private data channel or second system bus.

The X6-250M power consumption is 18W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation from -40 to +85C operation and 0.1 g2/Hz vibration. Conformal coating is available.

The FPGA logic can be fully customized using VHDL and Matlab and the Frame Work Logic tool set. The Matlab BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless and DSP functions such as DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available.

Software tools for host development include C++ libraries and drivers for Windows, Linux and VxWorks. Application examples demonstrating the module features are provided.

The XMC board can be used in a desktop PC using an adapter, or used in a Andale Data Logger, or used in an embedded PC, or external to a PC using eInstrument-DAQ.

Further information on Xilinx Virtex 6 FPGA’s.

  • Analogue to Digital Converter(s) = Linear Tech LTC2157-14 or LTC2158-14
  • FPGA = Xilinx Virtex6, XC6VLX240T or XC6VSX315T or XC6VSX475T
  • Digital to Analogue = N/A

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X6-250M the Adc memory is 4GB.

  • Wireless Receiver and Transmitter
  • LTE, WiMAX Physical Layer
  • RADAR
  • Medical Imaging
  • High Speed Data Recording and Playback
  • IP development

The product comes with the following support items to help you with your project:

  • Malibu Software, including
    • Snap – example application sourcecode to setup the board for acquisition and stream Adc samples to host file, written in C++.
    • Drivers for Windows/Linux, 32 and 64 bit.
  • Framework logic (source is extra cost)
    • Makes the X6 board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
  • iiForum
    • Knowledgebase of previous users of the X6 board.
    • Access to the X6 engineers.
  • Full hardware, software and firmware manuals as PDF.
  • Telephone/email technical support from EnTegra DSP and Innovative Integration.