X6-GSPS Data Acquisition Board with ADC12D1800 ADC and Virtex6 FPGA all on XMC

20 Years Experience

X6-GSPS 2 channel 1.8GSPS or single channel mode with 3.6GSPS 12 bit Adc, Xilinx Virtex6 FPGA and x8 lanes PCIe to host.
http://www.innovative-dsp.com/

PCIe XMC Module – National ADC12D1800 ADC functions as dual 1800MSPS or single 3600MSPS 12 bit ADC, Virtex6 FPGA and 4 GB Memory

FAQ
Made in USA, sold and supported in UK.
  • One National ADC12D1800
  • Functions as either single 3.6GSPS or dual 1.8GSPS 12-bit ADC channels
  • Xilinx Virtex6 SX315T/SX475T or LX240T
  • 4 Banks of 1GB DRAM (4 GB total)
  • Ultra-low jitter programmable clock
  • Gen2 x8 PCI Express providing 2 GB/s sustained transfer rates
  • PCI 32-bit, 66 MHz with P4 to Host card
  • PMC/XMC Module (75×150 mm)
  • 18-25W typical
  • Conduction Cooling per VITA 20
  • Environmental Levels for -40 to 85C operation, 9g RMS sine, 0.1g2/Hz random vibration
  • Adapters for VPX, Compact PCI, desktop PCI and cabled PCI Express systems

The X6-GSPS Data Acquisition Board integrates high-speed digitizing with signal processing on a PMC/XMC IO module for demanding DSP applications. The tight coupling of the digitizing to the Virtex6 FPGA core realizes architectures for SDR, RADAR, and LIDAR front end sensor digitizing and processing. The PCI Express system interface sustains transfer rates over 2 GB/s for data recording and integration as part of a high performance realtime system.

The X6-GSPS features two, 12-bit 1.8 GSPS ADCs that can be interleaved to use as one 3.6 GSPS digitizer. Analog input bandwidth of over 2.5 GHz supports wideband applications and undersampling. The sample clock is from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling and down-conversion.

A Xilinx Virtex6 SX315T (LX240T and SX475T options) with 4 banks of 1GB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates.

The X6-GSPS power consumption is 20W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation from -40 to +85C operation and 0.1 g2/Hz vibration. Conformal coating is available.

The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic tool set. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless, DSP and RADAR functions such as large-scale preintegrator, DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available.

Software tools for host development include C++ libraries and drivers for Windows, Linux and VxWorks. Application examples demonstrating the module features are provided.

The XMC board can be used in a desktop PC using an adapter, or used in a Andale Data Logger, or used in an embedded PC, or external to a PC using eInstrument-DAQ.

Further information on Xilinx Virtex 6 FPGA’s.

  • Analogue to Digital Converter(s) = National ADC12D1800
  • FPGA = Xilinx Virtex6, XC6VLX240T or XC6VSX315T or XC6VSX475T
  • Digital to Analogue = N/A

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X6-GSPS the Adc memory is 4GB.

  • Wireless Receiver and Transmitter
  • LTE, WiMAX Physical Layer
  • RADAR
  • Medical Imaging
  • High Speed Data Recording
  • IP development

The product comes with the following support items to help you with your project:

  • Malibu Software, including
    • Snap – example application sourcecode to setup the board for acquisition and stream Adc samples to host file, written in C++.
    • Drivers for Windows/Linux, 32 and 64 bit.
  • Framework logic (source is extra cost)
    • Makes the X6 board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
  • iiForum
    • Knowledgebase of previous users of the X6 board.
    • Access to the X6 engineers.
  • Full hardware, software and firmware manuals as PDF.
  • Telephone/email technical support from EnTegra DSP and Innovative Integration.