X6-RX Data Acquisition Board with ADC16DV160 ADCs and Virtex6 FPGA all on XMC

20 Years Experience

X6-RX 4 channels of 160MSPS 16 bit Adc with Xilinx Virtex6 FPGA and 8 lanes PCIe to host.
http://www.innovative-dsp.com/

PCIe XMC Module – Four 160 MSPS, 16-bit ADC16DV160 ADCs, Virtex6 FPGA and 4 GB Memory

FAQ
Made in USA, sold and supported in UK.
  • Four 160 MSPS, 16-bit ADC channels
  • Xilinx Virtex6 SX315T/SX475T or LX240T
  • 4 Banks of 1GB DRAM (4 GB total)
  • ADC16DV160 ADC’s
  • Ultra-low jitter programmable clock
  • Gen2 x8 PCI Express providing 2 GB/s sustained transfer rates
  • PCI 32-bit, 66 MHz with P4 to Host card
  • PMC/XMC Module (75×150 mm)
  • 18-25W typical
  • Conduction Cooling per VITA 20
  • Environmental Levels for -40 to 85C operation, 9g RMS sine, 0.1g2/Hz random vibration
  • Adapters for VPX, Compact PCI, desktop PCI and cabled PCI Express systems

The X6-RX Data Acquisition Board is a flexible IF receiver that integrates IF digitizing with signal processing on a PMC IO module. The module provides up to 48 configurable receiver channels with a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. With the X6-RX, IF recorders can log both the digitized raw data and channels real-time sustaining rates over 1 GB/s.

The X6-RX features four, 16-bit 160 MSPS A/D’s (ADC16DV160) with dual digital downconverters (DDC). IF frequencies of up to 300 MHz are supported. The sample clock is from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling and downconversion.

A Xilinx Virtex6 SX315T (LX240T at initial release) with 4 banks of 128MB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates.

Dual TI/GrayChip DDCs, connected directly to the FPGA, provide up to 48 narrowband or 8 wideband channels, with input from any A/D channel. The DDC perform complex or real downconversion, with flexible controls for mixing, filtering, decimation, output formats and data rates. Channels can be synchronized to support beam forming or frequency hopped systems.

The X6 family power is less than 15W for typical operation. VITA 20 conduction cooling is used with a heat-spreader and sink are Ruggedization levels for wide-temperature operation and conformal coating are supported.

The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic toolset. The MATLAB BSP supports real-time hardware-inthe-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP cores for DDC, demodulation, and FFT are available.

Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided.

This extremely versatile module is easily adapted for use in virtually any type of system. Our XMC carrier adapters offer conduction and convection cooling and are available for a range of interfaces including Desktop PCI, Desktop PCI Express, Cabled PCI Express, CompactPCI, and PXI/PXI Express. This module is also readily installed into Innovative Integration’s eInstrument Embedded PC, SBC-ComEx Single-Board Computer, and Andale Data Loggers.

The XMC board can be used in a desktop PC using an adapter, or used in a Andale Data Logger, or used in an embedded PC, or external to a PC using eInstrument-DAQ.

  • Analogue to Digital Converter(s) = ADC16DV160
  • FPGA = Xilinx Virtex6, XC6VLX240T or XC6VSX315T or XC6VSX475T
  • Digital to Analogue = N/A

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

On X6-RX the Adc memory is 4GB.

  • Wireless Receiver and Transmitter
  • LTE, WiMAX Physical Layer
  • RADAR
  • Medical Imaging
  • High Speed Data Recording
  • IP development

The product comes with the following support items to help you with your project:

  • Malibu Software, including
    • Snap – example application sourcecode to setup the board for acquisition and stream Adc samples to host file, written in C++.
    • Drivers for Windows/Linux, 32 and 64 bit.
  • Framework logic (source is extra cost)
    • Makes the X6 board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
  • iiForum
    • Knowledgebase of previous users of the X6 board.
    • Access to the X6 engineers.
  • Full hardware, software and firmware manuals as PDF.
  • Telephone/email technical support from EnTegra DSP and Innovative Integration.