PCIe XMC Module – Two channel 6 GSPS Dac, 16-bit and PLL, Kintex Ultrascale FPGA and 4 GB DDR4 Memory
- Two 16-bit, 6 Gsps, DAC channels:
- Single ended AC coupled outputs with programmable DC bias
- Differential DC model goal (TBD)
- 2.5 GHz analog bandwidth (1X)
- Digital inverse sinc filter
- Enhanced 2nd and 3rd Nyquist modes
- “Frequency doubling” 2X mode
- “Mixed” mode operation
- 48 bit NCO and 31 32bit fast hop NCOs
- Interpolation filters: 1X(bypassed)-64x
- Up to 6 GSPS streaming in 1x mode
- Internal or external clocking
- Internal 0.3 to 4.8 GHz PLL each DAC
- Triggering, fixed latency, synch.
- Xilinx Kintex Ultrascale FPGA XCKU0x0
- DDR4 DRAM in 2 banks each with 64 bit interface
- 4GB, increase to 8GB probable
- Up to 38.4GB/s total bandwidth (based on 100% data buss efficiency)
- QDR SRAM in 1 bank with 32 bit interface
- 4MB, 12x faster than DDR for random access applications (like FFTs)
The XU-TX is an XMC module with two 8 lane high speed serial links connected to the host (one on XMC connector P15, and one on P16). These links can support several protocols (up to 8 lane PCIe on P15 , Aurora, user defined, etc…). The standard XU-TX features two AC coupled single ended 16 bit DAC outputs with programmable DC bias. The Analog Devices AD9162 DAC devices employed support synchronization, interpolation, fixed latency and their unique output circuits allow improved frequency synthesis in the 2nd and 3rd Nyquist zones. This can shift the Nyquist null frequency in the output spectrum to two times the typical Nyquist null frequency.
A Xilinx Kintex Ultrascale FPGA XCKU060 with 4GB DDR4 RAM memory provides a very high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 7000 GMAC/s.
The XU XMC modules couple Innovative’s powerful Velocia architecture with two high performance 8-lane PCI Express links connected to the carrier, and a new XMC carrier which connects the 8 lane XU-TX links to the 16-lane carrier PCIe link using a PCIe switch, contact the factory for availability). Alternate protocol 8-lane links to a host are also supported by the XU-TX’s hardware using either P15’s or P16’s link to a compatible host.
The XU family can be fully customized using VHDL and MATLAB and the FrameWork Logic toolset. The MATLAB BSP supports real-time hardwarein-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.
IP logic cores are also available for SDR applications that provide multichannel modulations for PSK and FSK systems. These IP cores transform the XU-TX module into versatile transmitter, ready for integration into your application.
Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided, including streaming DAC samples from disk. The XU-TX can be used with the Andale high speed data record/playback system for arbitrary waveform generation from recorded data at sustained rates exceeding 6400 MB/s.
The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.
The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.
The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.
On XU-TX the Dac memory is 4GB.
- Wireless Transmitter
- LTE, WiMAX Physical Layer
- RADAR, ECM, Electronic Warfare
- High Speed Playback
- IP development
The product comes with the following support items to help you with your project:
- Malibu Software, including
- Arb, Snap, Wave & Stream – example applications as sourcecode to setup the board for acquisition and waveform generation. Shows designer how to stream Adc samples to host file and stream from host to Dacs, written in C++.
- Drivers for Windows/Linux, 32 and 64 bit.
- Framework logic (source is extra cost)
- Makes the XU board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
- Knowledgebase of previous users of the X6 board.
- Access to the XU engineers.
- Full hardware, software and firmware manuals as PDF.
- Telephone/email technical support from EnTegra DSP and Innovative Integration.