XU-RT

• Analogue to Digital Converter(s) =
• FPGA = Xilinx Kintex Ultrascale XCKU060/085
• Digital to Analogue =

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.

On XU-RT the Adc memory is 2GB and the Dac memory is 2GB.

The product comes with the following support items to help you with your project:

• Malibu Software, including
  • Arb, Snap, Wave & Stream – example applications as sourcecode to setup the board for acquisition and waveform generation. Shows designer how to stream Adc samples to host file and stream from host to Dacs, written in C++.
  • Drivers for Windows/Linux, 32 and 64 bit.
• Framework logic (source is extra cost)
  • Makes the XU board act as a data acquisition card, using onboard DDR as huge virtual FIFO’s.
• iiForum
  • Knowledgebase of previous users of the X6 board.
  • Access to the XU engineers.
• Full hardware, software and firmware manuals as PDF.
• Telephone/email technical support from EnTegra DSP and Innovative Integration.

These videos may be helpful in learning about using the FPGA on this board.

• Digital Receiver/Transceiver family
• XMC Family
• FPGA Basics
• Ultrascale PCI Express
• Memory Interface Generator
• Ultrascale Device Power