Overview
The VPX6-COP is a flexible FPGA co-processor card that integrates a
Virtex6 FPGA computing core with an industry-standard FMC IO module on a
3U OpenVPX card.
The FPGA computing core features the Xilinx Virtex 6 FPGA family, in
densities up to LX550 and SX475. The SX475 provides over 2000 DSP MAC
elements operating at up to 500 MHz. The FPGA core has two 9MB QDRII+ SRAM
banks, two 256MB LPDDR2 DRAM banks, and a 128MB DDR3 bank. Each memory is
directly connected to the FPGA and is fully independent.
For system communications, the VPX6-COP has a PCI Express and two
SRIO/Aurora interfaces. The PCIe port is a x8, Gen2 interface capable of
up to 2 GB/s sustained operation with 4 GB/s burst rate. Two additional x4
system ports support either SRIO, Aurora or custom protocols.
An FMC site, conforming to VITA 57, provides configurable IO for the
VPX6-COP. The FMC site has full support for the high pin count connector,
with over 80 LVDS pairs directly connected to the FPGA and x8 lanes at up
to 5 Gbps per lane. FMC also is readily adapted to application-specific
custom modules.
The VPX-COP family power is less than 15W for typical operation. The
card is available in conduction or air cooled versions. Ruggedization
levels supporting wide-temperature (-40 to 85C), humidity, and vibration
(up to 40 g shock, 0.1g2/Hz) may be specified (see table). REDI covers are
available for 2-level maintenance.
The FPGA logic can be fully customized using the Frame Work Logic tool
set. The toolset provides support for both MATLAB and RTL designs. The
MATLAB BSP supports real-time hardware-in-the-loop development using the
graphical, block diagram Simulink environment with Xilinx System
Generator. IP cores for a range of signal processing cores for
applications such as wireless, RADAR and SIGINT such as DDC, demodulation,
and FFT are also available.
Software tools for host development include C++ libraries and drivers
for VxWorks, Windows and Linux. Application examples demonstrating the
module features are provided. | 
