X3-2M ADC FPGA Board

PCI Express XMC Module with 12 simultaneous channels of 10 MSPS 16-bit A/D, and 1.8M FPGA with DSP

X3-2M XMC Module - 12 Channel 10MSPS ADCs and FPGA

Download Datasheet

Block Diagram

Malibu Libraries

Manufacturers Site

Manufacturers Full Catalogue

Framework Logic

FAQ's

RoHS Compliant C++ drivers available Works with Windows Ships with Malibu libraries Simulink/MATLAB Support Framework logic support Works with Linux

Adapters

eInstrument - DAQ Node

XMC to Cabled PCI Express Adapter

XMC to PCI Adapter Board

XMC to PCI Express Adapter Board

XMC to CompactPCI Adapter

SBC COMex Embedded PC

Chipset  
Analogue to Digital Converter(s) = AD7626
FPGA = Xilinx Spartan3A DSP – XC3SD1800A
Digital to Analogue Converter(s) = n/a
     

Features

  • 12 channels of 10 MSPS, 16-bit
    simultaneously sampling A/D
  • -110 dB noise floor, 91 dB SFDR
  • Low latency SAR converters
  • 50 ohm, differential inputs
  • Continuously acquire 12 simultaneous
    channels at 10 MSPS to system memory
  • Stream to system memory at up to 220MB/s
  • Xilinx Spartan3A DSP, 1.8M gate FPGA
  • 4MB SRAM
  • Sample clock is external or programmable, low jitter PLL
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 6 LVDS digital IO pairs on Front Panel
  • 44 bits digital IO on P16
  • Power Management features
  • PCI Express XMC Module (75x150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, or cabled PCI Express application

Applications

  • Multichannel sensor interface
  • Electronic Counter Measures (ECM)
  • Neuro-physical instrumentation
  • High speed motion recording
  • Spectral Analysis
  • RADAR

Overview

The X3-2M is an XMC IO module featuring 12 simultaneously sampling 16-bit, 10 MSPS A/D channels designed for high speed instrumentation and analysis for neuro-physical, high speed motion analysis, and high speed data acquisition applications.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA, 1.8M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express interface supports continuous data rates up to 220 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.