X3-SD16 ADC & DAC FPGA Board

PCI Express XMC Module, 16 Channel, 144ksps Adc, 192ksps Dac, 24-bit Analog Input & Output

X3-SD16 XMC Module - 16 Channel 144ksps 24 bit ADCs, 192ksps DACs and FPGA

Download Datasheet

Block Diagram

Malibu Libraries

Manufacturers Site

Manufacturers Full Catalogue

Framework Logic

FAQ's

RoHS Compliant C++ drivers available Works with Windows Ships with Malibu libraries Simulink/MATLAB Support Framework logic support Works with Linux

Adapters

eInstrument - DAQ Node

XMC to Cabled PCI Express Adapter

XMC to PCI Adapter Board

XMC to PCI Express Adapter Board

XMC to CompactPCI Adapter

SBC COMex Embedded PC

Chipset  
Analogue to Digital Converter(s) = TI ADS1278
FPGA = Xilinx Spartan3A DSP – XC3SD1800A
Digital to Analogue Converter(s) = TI PCM1681
     

Features

  • Sixteen Simultaneous Input Channels
  • 105 dB SFDR
  • -120 dB Noise Floor
  • Sixteen Simultaneous Output Channels
  • Differential instrumentation inputs with programmable +/-1, +/-5 and +/-10 V ranges
  • +/-10V output range
  • Programmable oversampling modes
  • Xilinx Spartan3A DSP, 1.8M gate FPGA
  • 4MB SRAM
  • Programmable PLL timebase
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 48 bits digital IO on J16
  • Power Management features
  • XMC Module (75x150 mm)
  • PCI Express (VITA 42.3)

Applications

  • Vibration Measurement
  • Audio and Acoustic Testing
  • Recording and Playback
  • Data acquisition

Overview

The X3-SD16 is an XMC IO module featuring sixteen 24-bit, 144 KHz A/D channels and sixteen 24-bit, 192 KHz DAC channels with FPGA computing core designed for servo controls, arbitrary waveform generation and stimulus-response applications. Very low-noise sigma-delta A/D and DACs support real-time vibration measurement, sonar and high-performance ultrasonic and audio applications.

Flexible trigger methods include N-point frames, software triggering and external triggering. The sample clock is either an external clock or on-board programmable PLL clock source. The PLL can lock to an external reference.

Data acquisition control, signal processing, buffering, and system functions are implemented in a Xilinx Spartan3A DSP 1.8M FPGA device. Two 512Kx32 memories are used for data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express interface supports continuous data rates up to 180 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.