In high performance FPGA based control, acquisition speed is not the only issue
In high performance FPGA based control, acquisition speed is not the only issue.
The ISI LLC X6-1000M 1GSPS Dual channel Adc and Dac with Virtex6 FPGA data acquisition card is still a winner for closed loop control such as LIDAR, Physics and Quantum Computing applications. Here is why…
The X6-1000M major features:
- Dual Texas Instruments ADS5400 12 bit 1GSPS Adc’s
- Dual Texas Instruments DAC5682Z 16 bit 1GSPS Dac’s
- Virtex6 FPGA XC6VLX240T or XC6VSX315T or XC6VSX475T
- 4 banks of 1GB DDR2 memory connected to the Virtex6
- Gen 2 x8 lane PCIe link to host with 3.5GB/s sustained full duplex
- Ultra low jitter programmable PLL and reference clock
- Choice of AC or DC coupling
The latest Adcs and Dacs from the major suppliers, Texas Instruments, Analog Devices, and Maxim Integrated that have 12 or more bits are virtually all moving to the JESD204B serial standard for the data interface. There are several advantages: this interface uses far fewer pins than parallel LVDS, makes layout easier and allows sample rates to reach 5GSPS and beyond with a 16 bit device, but the standard also has its disadvantages. It was years ago when an experienced RF consultant introduced me to the phrase “conservation of grief”. The truth is that when a solution is found to an engineering problem it often creates other problems elsewhere.
The problem with JESD204B as well as its complexity is that the link has significant latency at both the transmitter and receiver, and the latency can be different every time the link is reset and established. The internal latency for example of the AD9154 Dac is 17 PClock cycles where PClock is 1/40th the JESD204B bit rate, and the latency of the JESD204B port in the Xilinx library will also be long as the logic makes use of deep FIFO’s and SerDes components. An Adc using JESD204B will have the same issues, resulting in a total closed loop latency of ~1000ns for a 1GSPS Adc and Dac system. Some applications like LIDAR and Quantum Computing can not tolerate such high latency and variation. This would also impact phase stability and control.
The older LVDS interface does not have these issues. The X6-1000M Adc & Dac both use LVDS interfaces and has a total closed loop latency of 162ns, most of which is the pipeline latency in the converter stages themselves. The LVDS interface itself accounts for just a couple of clock cycles. These latencies are the same every system reset, whereas a serial standard like JESD204B can have some variation in the latency every time the link is established.
So for high performance closed loop control systems requiring high speed acquisition the trend towards SerDes interfaces is a disadvantage. There is merit in the LVDS technology though its limitations are the number of pins required for the interface.
For more information on the X6-1000M please see the datasheet page or call 01590 671700 to speak to an application engineer.
