XA-SDF

Features

• 4 x 24-bit, 2.5 MSPS Sigma-Delta A/D channels
• Input range ± 5V (Differential)
• 4.1 kO / 2.54kO Input Impedance (Differential / Single-Ended)
• 100 dB typ. Dynamic Range (2.5 MHz Output Data Rate)
• 100 dB typ. SNR (2.5 MHz Output Data Rate)
• -103 dB typ. THD (2.5 MHz Output Data Rate)
• Guaranteed monotonic to 24 bits; 0.00076% typ. INL
• Lowpass FIR filter with default or programmable coefficients
• DIO on P16 (18 differential pairs)
• Xilinx Artix-7 FPGA
• DDR3 Memory
• Precision on-board programmable or external reference clock
• Synchronized system sampling using common reference clock and triggers
• Front Panel External Reference and Trigger Inputs
• Framed, software or external triggering
• Log acquisition timing and events
• Power management features
• PCI Express 2.0 XMC Module (75×150 mm)
• Use in any PCI Express desktop, compact PCI/PXI, PXIe, or cabled PCI Express application
• Drivers for Windows, Ubuntu (NVidia Xavier, TX2), Centos

Chipset

• Analogue to Digital Converter(s) = AD7760
• FPGA = Xilinx Artix-7 XC7A200T2
• Digital to Analogue =N/A

Applications

• Industrial Automation and Controls
• Multichannel Data Acquisition Systems
• Scientific and Industrial equipment
• Test and Measurement

Useful resources on Youtube

These videos may be helpful in learning about using the FPGA on this board.

• XMC Family
• PXIe usage
• FPGA Basics
• Ultrascale PCI Express
• Memory Interface Generator
• Ultrascale Device Power

Overview

Analogue Front End

The XA-SDF is an XMC IO module featuring four 24-bit, sigma-delta ADCs capable of operating at output data rates of up to 2.5 MSPS. Timing is generated using an on-board PLL (LMK04806).
Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable precision clock source.

Artix-7

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Artix-7 FPGA device. Two 256Mb x16 DDR3 type memories provide data buffering and FPGA computing memory.
The logic can be fully customized using VHDL and the FrameWork Logic toolset. The PCI Express 2.0 interface supports data rates up to 1600 MB/s for unbuffered continuous data or burst data streams. When using a standard configuration involving DDR3 buffered data, a continuous data rate up to 1300 MB/s is supported.
18 Differential (LVDS) Digital IO (DIO) Pairs along with 4 pairs of RX/TX high-speed Serial Link lanes are available on the XMC P16 connector.

NVIDIA® Jetson GPU

The XA-SDF software support now includes drivers for development on the NVIDIA® Jetson TX2 GPU platform and the XVIDIA® Xavier that are aimed at Artificial Intelligence and is being increasing used in Photonics and Distributed Acoustic Sensing applications.