Artix-7 XMC Modules with Adc, Dac, FPGA, PLL, DDR3 DRAM, 4xPCIe 2.

XA XMC ARTIX-7 FPGA Modules

XA Data Acquisition modules are based around a Xilinx Artix-7 FPGA with 1024MB DRAM, FLASH and a four lane PCI Express (PCIe) 2.0 link to the host. The range includes boards with Analog to Digital Converters and Digital to Analog Converters. All boards have a PLL to generate a sample clock. The boards are XMC FPGA modules and can be fitted on a range of adapters to be used in desktop PC’s, compact PCI racks, VPX or external standalone boxes.

XA-160M Stimulus Response Dual 160MSPS 16 bit Adc, dual 615MSPS 16 bit Dac, Xilinx Artix-7 FPGA, DDR3, PCIe XMC module

Module	Adcs	Dacs	FPGA	DRAM
XA-500M	2 @ 500MSPS 14 bit	2 @ 615MSPS 16 bit	Xilinx Artix-7, 200T2	2GB
XA-160M	2 @ 160MSPS 16 bit	2 @ 615MSPS 16 bit	Xilinx Artix-7, 200T2	1GB
XA-RX	8 @ 125MSPS 16 bit		Xilinx Artix-7, 200T2	1GB
XA-AWG		8 @ 300MSPS 16 bit	Xilinx Artix-7, 200T2	1GB
XA-SDF	4 @ 2.5MSPS 24 bit		Xilinx Artix-7, 200T2	1GB
XA-Servo	16 @ 500ksps 18 bit	16 @ 2.5MSPS 16 bit	Xilinx Artix-7, 200T2	1GB

Design Methodology

The XA XMC FPGA range are aimed at high rate applications with sample rates from a few MSPS to 615MSPS. The cards have upto 8 channels of Adc and/or Dac which are all directly connected to the FPGA. The FPGA also has 1024MB of DDR3 memory connected to it and x4 PCIe lanes to the host via the XMC connector. There is a sample clock generation onboard where necessary using a low phase noise PLL which can use an internal or external reference. The boards come complete with logic and example software to enable the boards to be used out of the box for data acquisition and/or waveform generation applications. Full support is provided locally by Entegra Solutions Ltd. We have completed many custom designs with these boards and are well placed to advise and provide custom solutions. The factory logic is fully documented and includes projects for development in Xilinx Vivado.

There are drivers available to use the XA boards in LabVIEW and Matlab. The driver is a DLL that configures the clock, trigger and streaming on the board. Adc samples are streamed via the onboard DDR3 memory to the host for processing in the chosen tool. Dac samples are generated on the host in the chosen tool and streamed via onboard DDR3 memory to the Dacs. When the board has both Adcs and Dacs, eg XA-160M, each direction has 512MB of virtual FIFO (vFIFO) in DDR3. When the board is either just Adcs or just Dacs, the direction has 1024MB of vFIFO. This is necessary to decouple the fast devices from the relatively slower processing of the host tool.